Adding Fault-Tolerance to a Network-on-Chip

The constant reduction in the size of components of integrated circuits, as well as the growing operating frequency, increases the vulnerability to internal and external noise sources. These noises can cause a failure in any component, affecting the functioning of the system as a whole. Future Systems-on-Chip with dozens of cores will be based on Networks-on-Chip (NoCs), and will require networks that are able to detect a failure and avoid that this failure leads to a system failure and an application malfunction. In this context, this work aims at evaluating solutions to increase the reliability and availability of a SoCIN NoC, implementing mechanisms for error detection and correction on that network. The implemented mechanisms added a silicon overhead of 35,47% and a power dissipation overhead of 6,46% when compared to the original router. Keywords— System-on-Chip, Network-on-Chip, Faulttolerance, Error model, Single-event Upset